1) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof and, more particularly, to an improvement of a method for manufacturing a metal-insulator-semiconductor (MIS) transistor comprising a salicide structure with a second gate sidewall spacer and source/drain/gate contact pads.
2) Description of the Prior Art
A semiconductor device having a stacked structure of metal-insulator-semiconductor is called a MIS semiconductor device. A transistor using an oxide film as the insulator is especially called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). FIG. 1A shows a cross sectional structure of a typical MOSFET. The MOSFET comprises a pair of source/drain regions (n type for a N-MOSFET or p-type for a P-MOSFET) 12 on a surface of a silicon substrate 110, a gate oxide film 114 formed on the substrate between the source/drain 112, and a gate electrode 116 formed on the surface of the gate oxide film 114. A N-type MOSFET will be described but P-type MOSFET devices are equally relevant. The surface area of the substrate between the source/drain regions 112 is called a channel region 118. The length of the channel region 118 is distance between the source/drain regions 112.
In operation, a prescribed potential V.sub.D is applied between the source/drain 112. When a gate voltage V.sub.G larger than the threshold voltage V.sub.TH is applied to the gate electrode 116, an n type inverted layer where electrons are induced is formed in the channel region 118 for an n-MOSFET. Consequently, a drain current I.sub.D flows between the source and the drain 112. A depletion layer extends around the source and the drain regions 112.
To increase the speed of the transistor, the transistor structure is continuously being made smaller. The MIS transistor is miniaturized by shortening the channel length or forming source/drain regions having a shallow junction in accordance with a scaling rule in principle. However, two difficulties occur when making the transistor smaller, especially making the channel length shorter. First, short channel effects due to the shortening of the channel of the transistor becomes problematic. Because of the short channel effect, a breakdown phenomenon, and a hot electron effect are generated in the vicinity of the drain, so that reliability is decreased and the transistor performance is degraded. One of the short channel effects is the hot electron effect. A strong electric field is generated near the drain of a MISFET (MOSFET) having a short channel. Electrons introduced to this strong electric field region generate hot carriers by impact ionization. Some of the generated hot carders are caught by traps in the gate oxide film 114 of the MOSFET and are accumulated as time passes. The accumulated carders cause changes of the threshold voltage V.sub.TH with time and deterioration of mutual conductance, significantly reducing the reliability of the MOSFET.
The second difficulty encountered when miniaturizing the MOSFET transistor is that the wiring resistance of the source/drain impurity diffusion layer and gate electrode layer increase thereby reducing the transistor speed. At the source/drain regions, the resistance is increased as the junction depth becomes shallower and the conductive area becomes smaller. At the gate electrode, the resistance is increased as the gate length becomes shorter and the conductive area becomes smaller. Because of the increase in wiring resistance, the high speed responsiveness of the transistor is degraded.
As a structure for addressing these difficulties, a lightly doped drain (LDD) structure was adopted to prevent the short channel effect and, in addition, as a structure for preventing the increase in wiring resistance, a salicide structure was proposed. FIG. 1B is a diagram of a conventional MIS transistor having such structure. A n-type FET device is described below but p-type devices are also possible.
Referring to the FIG. 1B, a gate electrode 116 comprising polysilicon is formed on a silicon substrate 110 over a gate oxide film 114. Sidewall spacers 120 serve as insulating films are formed on either side of the gate electrode 118. N&lt;-&gt; impurity regions (i.e., lightly doped source/drain regions) 122 with low concentration are formed at a self-aligning position with the gate electrode 116 on the p type silicon substrate 110 or well. In addition, n&lt;+&gt; impurity regions (i.e., highly doped source/drain regions) 124 with high concentrations are formed at a self-aligning position with the sidewall spacers 120. Each n&lt;-&gt; impurity region 122 and n&lt;+&gt; impurity region 124 constitutes a source and drain region 122 124 of the transistor. In addition, a structure of the impurity region having a structure in which the positions of the n&lt;-&gt; impurity region 122 with low concentration and the n&lt;+&gt; impurity region 124 with high concentration are offset is referred to as a lightly doped drain (LDD) structure.
Also, silicide layers 130 comprising titanium silicide are formed on the upper surface of the gate electrode 116 and the surface of the highly doped source/drain regions 24. The structure of the silicide layers 130 132 that are formed in a self-alignment manner on the gate electrode 116 and the highly doped source/drain regions 124 is referred to as a "salicide structure".
The lightly doped source/drain impurity regions 122 constituting the LDD structure are positioned such that the impurity concentration distribution between the highly doped source/drain regions 124 and a channel region 118, just beneath the gate electrode 116, may be made gently sloping. As a result, the electric field concentration, particularly on the side of the drain region, is mitigated and the generation of the breakdown phenomenon and hot carriers are restrained.
In addition, the silicide layers 130 132 constituting the salicide structure have a higher conductivity. The wiring resistance of the gate electrode 116 and the sheet resistance of the source/drain regions 122 124 are reduced.
Referring to FIG. 1B, a description is made of manufacturing steps of the conventional LDD MOS transistor. A thin gate oxide film 114 is formed on a p type silicon substrate 110. Then, a polysilicon layer is formed on the surface of the gate oxide film 114 to form a gate electrode 116 by patterning the gate oxide film 114 and the polysilicon layer. N type impurity ions are implanted on the p type silicon substrate 110 with a small dosage using the gate electrode 116 as a mask to form n&lt;-&gt; impurity regions 122 and 22.
Next, a silicon oxide film of the thickness approximately equal to about 2500 Angstrom is formed on the p type silicon substrate 110 on which the gate electrode 116 was formed. Then, sidewall spacers 120 are formed on either side of the gate electrode 116 by anisotropic etching the silicon oxide film. Next, the n type impurity ions are implanted into the p type silicon substrate 110 with a large dosage using these sidewall spacers 120 and the gate electrode 116 as a mask to form highly doped source drain regions 24.
A refractory metal layer, such as titanium, is evaporated on the surface of the silicon substrate 110, the gate electrode 116, and the sidewall spacers 120. Thereafter, high temperature heat treatment is performed and the refractory metal layer is made to react with the polysilicon layer of the gate electrode 116 and source/drain regions 130 in contact with the refractor metal layer to form a silicide layer.
Next, the unreacted refractory metal layer evaporated on the surface of the sidewall spacers 120 is removed. Silicide layers 130 132 are formed in a self-alignment manner on the surface of the gate electrode 116 and the highly doped source drain regions 124.
The sidewall spacers 120 fulfill two functions. First, they function as a mask to selectively form the silicide layer of the refractory metal layer. Theoretically, the sidewall spacers are not supposed to react with the refractory metal layer 130 132. The silicide regions on the top surface of the gate electrode 132 and on the source/drain regions 130 are separated by the sidewall spacer and self-aligned.
However, as shown in FIG. 1C, with the conventional process, silicon can diffuse over the spacers 120 from the source/drain regions 124 and the gate electrode 116. The diffused silicon will react with the titanium over the spacers 120, thus forming a titanium silicide bridge (stringer) 131 over the spacers 120. This titanium silicide formation over the spacers is called a "stringer" or "bridging problem". The bridging problem reduces device yields by electrically shorting the source/drain 124 to the gate electrode 116. The silicide rapid thermal anneal must be tightly controlled to minimize the silicon diffusion which causes the stringer 131 or bridge formation.
Second, the sidewall spacer 120 functions to define the offset length of the n&lt;-&gt; impurity region 122 and n&lt;+&gt; impurity region 124 of the source and drain region. That is, the length of the n&lt;-&gt; impurity region 122 is substantially defined by the film thickness of this sidewall spacer 120. However, in practice the minimum thickness of the sidewall spacer 120 is limited by the requirement to separate the silicide regions 130 132, so the minimum length of the lightly doped source/drain region 122 is also limited. In the conventional process, the minimum sidewall spacer thickness is determined largely by the rapid thermal anneal temperature and times, i.e., the higher temperature and longer the anneal, the thicker the spacer must be.
As semiconductor technology reaches the quarter micron device size, two major problems are encountered using the conventional silicide process--(1) silicide spiking and leakage in shallow source/drain regions and (2) silicide stringers/bridging. First, to increase transistor speed, the distance between the source/drain and gate regions must be reduced, but at the same time the silicide layers 130 and 132 must be electrically isolated (not shorted together). By reducing the distances, the parasitic resistance of the lightly doped source/drain is reduced, thus increasing the transistor speed. However, a reliable simple manufacturing process must be developed that further reduce transistor size while ensuring that the silicide bridge problem 131 does not short out the source/drain 124 to the gate electrode 116.
The second problem with 0.25 .mu.m technology is that the source/drain junction depth must be reduced to improve short channel effects. However, salicidation causes severe silicon substrate consumption in S/D areas (e.g., spiking 130A in FIG. 1C), resulting in junction leakage. There is a need to develop a process that prevent silicide spiking will allowing for shallow source/drain regions and low resistance silicide contacts.